1. Field of the Invention
The present invention relates to a device for maintaining synchronization of a plurality of field programmable gate arrays (FPGAs), and more particularly, to a device for maintaining synchronization of a plurality of FPGAs which can easily and precisely maintain the synchronization of the plurality of FPGAs in a device in which two or more FPGAs are interactively connected and operated.
2. Discussion of Related Art
As well known, a field programmable gate array (FPGA) is a semiconductor device including a programmable logic element and an internal line, and a user can implement a desired device by programming a FPGA chip in a state in which the FPGA chip is installed on a board. The FPGA configures a combinational logic using a look-up table (LUT) instead of simple gates such as an AND gate, a NAND gate, an OR gate, and a NOR gate, and can implement a sequential logic since flip-flops are connected in the output stage of the LUT.
In addition to the LUT, the FPGA further includes an adder/multiplier for calculation, a phase locked loop (PLL) block for providing clocks with various forms in the FPGA, a high-speed serial input/output such as a peripheral component interconnect-Express (PCI-Express) or a serial advanced technology attachment (SATA), a central processing unit (CPU) for processing complex calculations, a memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), an Ethernet media access control (MAC), etc. The FPGA has been applied in various fields such as a digital unit (DU) for processing a digital signal or a radio unit (RU) for processing a radio signal, etc, of a digital signal processor (DSP), an initial version of an application specific integrated circuit (ASIC), a computer hardware emulator, a baseband emulator, or a centralized/cloud radio access network (CRAN).
Meanwhile, when implementing a device requiring a large amount of logic using the FPGA, for example, the DU or the RU of the CRAN, it may not be sufficient to implement the device using only one FPGA, and in this case, the device may be implemented using a plurality of FPGAs. Accordingly, when constituting the device using two or more FPGAs, the device may be interactively and easily operated only when precisely maintaining synchronization of all FPGAs.
In the device including the two or more FPGAs, a conventional method for maintaining the synchronization of the FPGAs may simultaneously provide a trigger signal by a trigger signal generator for all FPGAs and independently match the synchronization in each of the FPGAs in a state in which the trigger signal generator is separately provided from the device. However, this method has a problem in which costs of the device are increased and also a size of the device is increased since the trigger signal generator is separately provided.
On the other hand, there is a method of adding synchronization information in a header and transmitting the header to a data line. In this case, there is a problem in which data throughput is lowered due to the addition of the synchronization information in the header.